Decision Feedback Equalization (DFE) is based on the principle that once the value of the current transmitted symbol has been determined, the contribution of intersymbol interference (ISI) to future received symbols can be removed. DFE has a nonlinear feature that is due to a decision device that attempts to determine which symbol of a set of discrete levels was actually transmitted. Once the current symbol has been decided, a filter structure calculates the ISI effect it would tend to have on subsequent received symbols and, thereafter, compensate the input to the decision device for subsequent samples. This post-cursor ISI removal is accomplished by the use of, among other things, a feedback filter structure.
Such a feedback filter structure can include a multiple tap digital filter for cancelling, for example, post-cursor ISI and transmission channel discontinuity. In typical implementations, the second or higher taps of a multiple tap implementation have negative or positive feedback depending on transmission channel characteristics. In certain implementations the second taps and above of a DFE have independent programmable polarity control. For example, polarity control can be implemented to select either DFE delayed data or inverted delayed data by implementing a 2-to-1 multiplexer in the critical path. Such implementations, however, can introduce challenges when attempting to meet the needs of higher speed circuits. For example, feedback loop timing can be difficult to meet. The delays introduced by the multiplexer, for example, can make it difficult to meet system requirements.
There exists a need in the art for a DFE with reduced loop timing. There is a further need in the art for DFE implementations with reduced hardware complexity that still meet operational and timing requirements.